I took the PCM1742 as an example. Page 12 describes the Audio Serial Interface, and from what is stated, it seems the VOUT is going to be at the bipolar zero level of Vcc/2, but only after BCK is reintroduced (and assuming LRCLK and SCK also present). During the period where BCK is inactive, the assumption is that VOUT remains at its last value:
Accordingly, internal operation of the device is suspended when the sampling rate clock of LRCK is changed or SCK and/or BCK is interrupted at least for three bit-clock cycles. If SCK, BCK, and LRCK are provided continuously after this suspended state, the internal operation is resynchronized automatically within a period of less than 3/fS. During this resynchronization period and for a 3/fS time thereafter, the analog output is forced to the bipolar zero level, or VCC/2.
From this description, I am not absolutely sure this is the case, so I'll get with the product group to find out.
-Leonard
