Forum Post: RE: AIC3104 DAC output switching

Hi Don,

Thanks for replying.

Does my register-writing function I2CRegWrite() work correctly?

Can't be 100% sure but in general I am getting the AI3104 to behave as I intend - changes in values written to registers have the anticipated effects on routing, gain settings, etc. So I am pretty confident of that mechanism.

Am I writing to the registers in the wrong order, or writing incorrect values, or relying on default values that are not
correctly implemented?

I suspect that this is the problem.

Since my last post I have found that I can get the problem even if using DAC3 - it depends what you write to registers 81,82,84,85,88,89,91,92.
 
My test setup is that I am inputting sinusoids of around 500mVp-p magnitude and of different frequencies to LINE1LP and LINE1RP. A microcontroller is running a program that copies DOUT to DIN. Using DAC3 I see the two sinusoids on LEFTLOP and RIGHTLOP as expected. When I make the configuration changes I see the expected sinusoid output on RIGHTLOP but the LEFTLOP output comprises the expected sinusoid (from  LINE1LP) plus the sinusoid from LINE1RP (at about 10% magnitude compared to output on RIGHTLOP).

The configuration below appears to work for me. Writing 0x50 to register 41 selects the DAC3 option, in which case the writes to  registers 81,82,84,85,88,89,91,92 should be irrelevant? (all default 0x00).

However, I can cause my problem (even using DAC3) simply by writing 0x80 to register 82. DAC_L1 into LEFTLOPM Volume control.

Writing 0x80 to register 16 (mute right ADC PGA) has no effect on the LEFT output - it still contains an element of right input (but of course means no right channel signal).

Leaving register 22 to its default (LINE1RP not connected to ADC PGA) does eliminate the problem (but of course means no right channel signal).

One thing that I do not understand is why it is necessary to set bit 0 in registers 86 and 93 - the datasheet lists these bits as read only.

So is the problem in the LEFTLOPM volume control mixer? Is it letting through some PGA_R when it shouldn't, i.e. when regs 81,84,85 are zero but when reg 82 (DAC_L1)
is enabled?

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 0, 0x00); // select registers in page 0
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 1, 0x80); // reset codec

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 2, 0xAA); // fsref divisors
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 3, 0x10); // PLL disable Q = 2 -> fsref 48kHz
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 7, 0x0A); // datapath setup and fsref 48kHz

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 8, 0xC0); // codec is BCLK and WCLK master

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 9, 0xC0); // left justified mode 16 bit per channel
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 10, 0x00); // no data offset

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 15, 0x00); // left input PGA gain 0dB
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 16, 0x00); // right input PGA gain 0dB

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 19, 0x04); //
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 22, 0x04); //


// configure output

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 81, 0x00 );
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 84, 0x00 ); // PGA_R to LEFT LOPM mixer
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 85, 0x00 );
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 91, 0x00 );
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 88, 0x00 );
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 89, 0x00 );

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 82, 0x00 ); // DAC_L1 to LEFT LOPM mixer
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 92, 0x00 );

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 41, 0x50); // DAC_L3, DAC_R3 to LINE OUT


  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 86, 0x09 ); // WHY DOES BIT 0 HAVE TO BE SET?
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 93, 0x09 );

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 43, 0x00); // Left DAC Digital Volume Mute=OFF, Gain=0dB
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 44, 0x00); // Right DAC Digital Volume Mute=OFF, Gain=0dB

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 37, 0xc0); // power up left and right DACs and HPLCOM=SingleEnd

  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 101, 0x01); //
  I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 102, 0x00); //