Hi Harry,
At the center of you problem is the fact that the internal sampling capacitor is not discharged between samples. In essence the sample acquired from Ch4 is still there when acquiring Ch7. You have to give the sampling capacitor enough time to settle between samples.
Here a couple of approaches you can take:
- extend the Track period - Track is the only time when the sampling capacitor is connected to the source. This can be easily done in the FPGA (slow the SCLK during Track), but not so easy with the uC.
- slow down the SCLK for the whole SPI transaction
- reduce the impedance of the source driving the input channel
- double sample the channel and discard the first sample
Hope this helps,
Sincerely,
tom