We are currently designing and evaluation platform using a adc12d1800rf evaluation board connected to an Altera FPGA card through the FMC connector. The idea was to minimize the pin count and therefore use just a single channel with non-des, non-demux mode, so only 12 data bits. With this configuration, we were hoping to run the ADC at 1044.48 MHz. I can't find anything in the data sheet of the ADC or that of the evaluation board that suggests a limitation on the data rate of each port. However, I happen to know that the Virtex 4 has a maximum speed of 1 gbps on it's high speed ports. So in my opinion, a data rate of 1044.48 Msps from a single channel should be possible from the ADC but is in this case limited by the Virtex 4 on the evaluation board. Is this a correct observation? And if so, it might be useful to add this information in the datasheet of the evaluation board.
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