Dear all,
I found the documentation of the LMP90100 chip really deficient regarding the description of how the ODR works in a multi-channel configuration. I would be grateful if somebody from TI could shed some light on the following points.
1) Why the manual keep talking about one single ODR if the ODR is a channel-based property? What ODR shoud I assume if I have two channels with different ODR?
2) What happens to the DRDYB signal when two channels are set to two different ODR?
3) What happens to the DRDYB signal when two channels are set to the same ODR? Can I assume the chip will return the sequence Ch0, Ch1, Ch0, Ch1, ...?
4) Why in the description of figure 52 (of the chip manual) it seems that DRDYB is set low by the electronics to signal that a data sample is ready and set high when the data is fully read while figure 61 suggests the opposite, that DRDYB is set high to signal that a sample is ready and set low after an unspecified while? Does DRDYB work in negated logic or not? Which picture is wrong?
5) I have an application where each one of 4 LMP90100 read two differential channels. The chips are configured in the same way: channel 0 and channel 1 are read continuously using ScanMode2 with the same ODR = 13.67 Hz, DRDYB is routed to D6 and used as an interrupt source. My ISR detects the interrupting chip, reads the file register from 0x19 to 0x1C (included) into a buffer and counts how many times it has been called for channel 0 and 1. I would expect to see the counters differ at most by one unit, but surprisingly the two counts can differ much more. In fact sometimes one of the two channels is never read. This is very annoying. How would you explain that and how can I change this behaviour?
Sincerly,
Anton