Satoshi-san,
some comments:
0x00 = 0x30. The DAC is set up in HP/HP mode with x4L mode. Please make sure the input bandwidth and output bandwidth requirement in Table 9. Attached is the spreadsheet for customer to calculate frequency planning.
0x01 = 0x09. x4L mode, FIFO bypassed, inv_pll_lock = 0, dual clock mode. Please make sure the timing between CLK1 and CLK2 are tightly controlled since the FIFO is not used to absorb phase offset between the two clocks. Follow table 2, 4th option for detail. I am assuming PLLVDD is 0V since PLL is not used at this point.
0x02 = 0x20. dual clock mode, offset binary. Same guidance above.
0x03 = 0x00 NCO off.
0x0C = 0x00 - no need to write since NCO is off.
0x1C = 0x01 - phstr_clkdvi_sel = 1. It is really a test mode. I don't see a harm programming this.
0x17 to 0x19. Programming gain A and gain B
Overall, I think the register settings are fine. Please ask the customer to double check the input/output bandwidth requirement. Also, please ask them to pull TXENABLE high after the registers are programmed to start the DAC transmission.
-Kang