Hi,
I am waiting exact confirmation from our design team, but from looking at the schematics for the EVM I would have to say that the ALIGN input signal is LVPECL. The DACCLK is LVPECL, and on the EVM the DACCLK and ALIGN signals come from the same clock chip, with identical termination, AC coupling, and biasing.
The datasheet for these DACs is being updated at this time, and one of the things missing in the datasheet is a section for the electrical specs for the LVPECL inputs (things like differential voltage requirements, etc). But the datasheet for the DAC3283 lists details for the LVPECL inputs and these details will be the same for the DAC31x4 devices. See page 8 of that datasheet for the electrical specs and Figure 50 Page 44 of that datasheet for the equivalent input circuit for the LVPECL inputs. (By the way, in the DAC3183 datasheet, the ALIGN signal is called OSTR and is LVPECL just like the DACCLK.)
The LVPECL inputs are not internally terminated, but *are* internally biased if the signals are AC coupled. If your LVDS driver can tolerate an AC coupled path for the ALIGN signal, then AC coupling and terminating into a 100 ohm termination should be sufficient, with the DAC then internally biasing the swing to the desired level that the DAC wants to see it at.
Regards,
Richard P.