Hi,
The sample data bits and the DRY clock siignal *do* transition at the same time, as illustrated in Figure 1 of the datasheet. If you look at these signals with a couple channels of a scope at the pins of the ADC you should see them transition togehter to within some tolerance. But if you use chipscope to look at the clock and data inside the FPGA *after* the IDELAY cells and after buffering in the FPGA then you will likely see something else.
the clock input is relatively high impedance as seen in Figure 57 of the datasheet with about a 1Kohm biasng to the desired common mode voltage. So no, not much loading. But external to the ADC on the EVM is a termination resistor to terminate the 50 ohm coax that is usually used to bring a clock signal into the EVM. If you are using a single-ended CMOS output from the FPGA for the clock source then these FPGA outputs are not made to drive a 50 ohm load and the signal will be loaded down significantly.
Regards,
Richard P.