Forum Post: RE: AFE7222 - external pull up resistance and pull down resistance on LVDS pin

Hi Ebenezer San,

Thank you for your update!

<Q1>
In general, how much of pre-bias voltage is required? 25mV?
(Vidh and Vidl are 350mv, so it seems that differential noise margin is enough values)

<Q2>
About settings of Pin INN_B_ADC, INP_B_ADC, our cusomer use only 1CH.
How should non-use of INN_B_ADC, INP_B_ADC treat? 
Our cusotmer use 100Ω for terminator(terminal resistance).
Is this setting correct, or not?
And then, how should the setting of resister do? - is not required?

We need your help.

Kind regards,

Hirotaka Matsumoto