Hi Shinichi,
This response is not unexpected. There are essentially three events happening here.
- The DAC is powered on and the output latches assume some default value, which is undefined. So the startup scenario is expected.
- The rising edge on the clock due to the FPGA config latches in the digital data presented at the data pins, either all 0's or all 1's, depending on when your data switches relative to the clock.
- The DAC output updates with the new value on the clock falling edge that occurs at the end of the FPGA configuration.
In order to start the DAC with a default output, I believe they will need to hold the PD pin high during startup. Once the FPGA is configured, the data should be set to the desired starting condition and the clock should be run. After one clock cycle the latches should be updated and the PD pin can be set low to begin normal operation.
Secondly, I would suggest using the same load on both outputs. So if they have 60Ω on IOUTp, then IOUTn should also have 60Ω.
Regards,
Matt Guibord