Hi,
I'm using tlv320aic3204 and tms320f2811, and here is some information of my system :
(1) fs_adc=fs_dac=8KHz.
(2)CODEC_CLKIN is connected to MCLK, which is provided by an external 12.288Mhz oscillator.
(3)2811 using I2C config aic3204, and verified the accessing correctness by reading registers back.
(4)adc/dac loopback mode works fine by setting bit4 of register page0/reg29.
(5)aic3204 using dsp mode to transfer voice data with 2811's mcbsp. and data offset both set to 1 cycle.
(6) Inside 2811, trying to do: receiving one frame from mcbsp, then send back to mcbsp, one by one. Now the problem is it doesn't work in this way, i can hear nothing but noise.
Belowing is my configuration code:
// software reset
WriteCodecReg(0x18, 0x00, 0x00); // select page 0
WriteCodecReg(0x18, 0x01, 0x01); // reset codec
DelayMs(10);
// configure power supply
WriteCodecReg(0x18, 0x00, 0x01); // select page 1
WriteCodecReg(0x18, 0x02, 0xa9); // Power up AVDD LDO
WriteCodecReg(0x18, 0x01, 0x08); // disable crude avdd genratation from dvdd
WriteCodecReg(0x18, 0x02, 0xa1); // enable analog blocks, use ldo power
WriteCodecReg(0x18, 0x0a, 0x00); // common mode confige: 0.9v, full chip common mode
// ??? power tune config
// ??? MicPGA startup delay
WriteCodecReg(0x18, 0x47, 0x32); // Set the input power-up time to 3.1ms (for ADC)
WriteCodecReg(0x18, 0x7b, 0x01); // Set the REF charging time to 40ms
// pll and clocks divider configuration and power up for 8k sample rate
WriteCodecReg(0x18, 0x00, 0x00); // select page 0
WriteCodecReg(0x18, 0x04, 0x00); // MCLK pin is CODEC_CLKIN
WriteCodecReg(0x18, 0x05, 0x00); // PLL power down
WriteCodecReg(0x18, 0x0b, 0x82); // powerup NDAC and set NDAC = 6/3
WriteCodecReg(0x18, 0x0c, 0x82); // powerup MDAC and set MDAC = 2
WriteCodecReg(0x18, 0x0d, 0x01); // hi_byte of DOSR
WriteCodecReg(0x18, 0x0e, 0x80); // lo_byte of DOSR, DOSR = 128*3
WriteCodecReg(0x18, 0x12, 0x86); // powerup NADC and set NADC = 6
WriteCodecReg(0x18, 0x13, 0x82); // powerup MADC and set MADC = 2
WriteCodecReg(0x18, 0x14, 0x80); // AOSR=128: use PRB_R1 to PRB_R6, ADC filter type A
// fs = 12.288M/(2*6*128) = 8K
WriteCodecReg(0x18, 0x1d, 0x04); // BDIV_CLKIN = DAC_CLK
WriteCodecReg(0x18, 0x1e, 0x86); // pwerup BCLK N divider and set to 8
// BCLK = 12.288/2(NDAC)/6 = 1024k
WriteCodecReg(0x18, 0x1b, 0x4d); // dsp interface, 16bit, wclk and bclk output
WriteCodecReg(0x18, 0x1c, 0x01); // data offset = 2 bclk
DelayMs(10);
// processing blocks configuration
WriteCodecReg(0x18, 0x00, 0x00); // select page 0
WriteCodecReg(0x18, 0x3c, 0x02); // select PRB_P2
WriteCodecReg(0x18, 0x3d, 0x02); // select PRB_R2
// adc routing and power up
WriteCodecReg(0x18, 0x00, 0x01); // select page 1
WriteCodecReg(0x18, 0x34, 0x80); // Route IN1L to LEFT_P with 20K input impedance
WriteCodecReg(0x18, 0x36, 0x80); // Route CM1L to LEFT_M with 20K input impedance
WriteCodecReg(0x18, 0x37, 0x80); // Route IN1R to RIGHT_P with 20K input impedance
WriteCodecReg(0x18, 0x39, 0x80); // Route CM1R to RIGHT_M with 20K input impedance
WriteCodecReg(0x18, 0x3b, 0x0c); // left MICPGA gain = 6dB
WriteCodecReg(0x18, 0x3c, 0x0c); // right MICPGA gain = 6dB
WriteCodecReg(0x18, 0x00, 0x00); // select page 0
WriteCodecReg(0x18, 0x51, 0xc0); // powerup left and right adc
WriteCodecReg(0x18, 0x52, 0x00); // unmute left and right adc
// dac routing and power up
WriteCodecReg(0x18, 0x00, 0x01); // select page 1
WriteCodecReg(0x18, 0x14, 0x25); // De-pop: 0.5 time constants, 6k resistance
WriteCodecReg(0x18, 0x0c, 0x08); // left DAC to HPL
WriteCodecReg(0x18, 0x0d, 0x08); // right DAC to HPR
WriteCodecReg(0x18, 0x0e, 0x08); // left DAC to LOL
WriteCodecReg(0x18, 0x0f, 0x08); // right DAC to LOR
WriteCodecReg(0x18, 0x09, 0x3c); // Power up HPL/HPR/LOL/LOR
WriteCodecReg(0x18, 0x10, 0x0C); // unmute HPL, 6dB gain
WriteCodecReg(0x18, 0x11, 0x0C); // unmute HPR, 6dB gain
WriteCodecReg(0x18, 0x12, 0x0C); // unmute LOL, 6dB gain
WriteCodecReg(0x18, 0x13, 0x0C); // unmute LOR, 6dB gain
DelayMs(10);
WriteCodecReg(0x18, 0x00, 0x00); // select page 0
WriteCodecReg(0x18, 0x41, 0x00); // left dac gain = 0dB
WriteCodecReg(0x18, 0x42, 0x00); // right dac gain = 0dB
WriteCodecReg(0x18, 0x3f, 0xd6); // powerup left and right dac, select dac datapath
// soft-stepping disable
WriteCodecReg(0x18, 0x40, 0x00); // Unmute LDAC/RDAC
Note: 0x18 actually is 0x30 when sending to the device.
Can you guys help me out of this problem?
thanks,
Weslly