Hey,
One concern I have with this ADC is the fact that the datasheet specifies it has LVDS compatible I/O’s but the LVDS buffer supply is specified as 3.3v. Usually LVDS is specified at 2.5v. If I am driving true LVDS inputs on the FPGA do I have a concern with voltage level mismatch? I assume this is taken care of in the part but could you check?
There are no max voltages defined for teh L\VDS outputs only typicals.
Cheers
calum
