Hi Chris,
Thank you for your prompt response.
SCLK is 2MHz. I did not record SCLK and CS. Overall reading is ok.
Originally, I set START as high always. Now, I pulses START, as Bob suggested. But I guess it needs a circuitry to generate the START signal upto the requirements. For simplicity, I handles START in firmware code. When DRY is triggered, START is set to low. After data is read, it sets to high for the next channel, but not at the end of cycle. With min 8 cycles of Tsdsu setup time, it makes START complicated, beacuse of the external DRY, ISR, 2 or more cycles per second. As far as the last DRY is not ready, because the START and read GPIO at the end of the cycle.
Because the START is handled by firmware, it is also hard to set further apart with DRY.
I think I probably stick with current way without adding extra complexcity.
Thank you,
David