Hi Richard,
Thanks a lot for the quick reply. I had gone through the application note you had sent. I shall look into it once again, and try to note the principles illustrated therein.
In the meantime, it would also be great if you could provide me with vhdl code for the TSW1200, so that it would help me get a better idea of the principles implemented. With respect to the design you had posted, I understand that IDELAY could be put up in the clock lines so as to account for the delays introduced by the device lines ( Am I right?). But, why should the data lines too need the IDELAY?
Thanking You,
Basil M.