Hi Anil,
I will recommend the 250MHz clock input so you can bypass the internal divider since synchronization is your main concern. You can refer to the thread below for a discussion on this:
http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/320706.aspx
However, if some components on your system require 500MHz or 1GHz, then it is advisable to provide this frequency as the input to the ADC and use the internal divider. This will help reduce the harmonics in your system. The ADC performance will be the same, regardless of the clocking option.
The design package has an example drive circuit for the ADC clock on sheet 1 of schematic. You can download from here
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slrr004&fileType=zip
Thanks,
Eben.