Hello
Is it a known behaviour of this audio ADC ?
Because it is difficult to have a system clock already present at power up.
In our system the system clock is coming from a FPGA and is not present straight at power raising up but a few hundred of milliseconds later.
Once the system clock starts, the dataout is available at DOUT pin without problems, but one of the channels is stuck at 0x7FFF value.
Best regards,