Hello Chris,
Thank you for all your answers and explanations, below are my comments and follow up questions.
About Ans1- you answered my question, thank you!
About Ans2- Allow me to explain you my interpretation of your answer to Q2. If an analog signal presents itself at the input at (t=0) its settled digital equivalent will present itself after the 62nd /DRDY pulse ~ 1sec later.
Q4.How much off is the value at the digital output at the 1st /DRDY, 2nd /DRDY..... pulse?
About Ans3- Just to make sure, you mean the external clock that I am applying to the RESET pin. Should be 62.5Hz X N (N =1,2,3,....).
Response to your comments;
In our application the ADS1281 will be controlled with an FPGA in a state machine configuration, causing us to choose the PINMODE configuration for the ADS1281.
Q5. Regarding your screenshot comment, please explain, in PINMODE, which clock input (CLK or SCLK or /RESET) generates directly or indirectly the /DRDY output?
Thanks again,
AD