Jim, I have another question about the ADS54J66 's datasheet, it make me feel puzzled. About this data flow diagram question, i spend some time to draw some drafts to make my question more clear. there are be named " ADS54J66 A" ， “ ADS54J66 B” ， “ ADS54J66 C”. I post them below. these question are related to the OPERATION MODE 8. Q1 > The three data flow diagrams below from ADC outputs data stream to the JESD204B output bit stream, which one is the correct understanding? If none of them is right, please help me confirm which one is closest to the right answer. Q2 > I tend to think that " ADS54J66 A" is right, but in the datasheet (page 38, table 14), the subtable (named LMFS = 4421( 0-pad )) which is related to the operation mode 8, there are 16bits 0 fallow A0[15:8] A[7:0], i don't know these zeros come from where ? So i drawed the daft B and C. Q3 > About the “ ADS54J66 B”, i think may be the serdes Rx or the JESD204B Rx register is 32 bits ,so when they deal the 16bits data, they must append 16bits zeros. so i can ignor these zeros? So, when i desgin the FPGA receiver, i should also use a 32 bits register to get this data, and just ignor the low-16bits? Q4 > About the “ ADS54J66 C”,i also doubt its correctness, because it even use 20Gbps. Q5 > The red line in “ ADS54J66 B”, can i think the data at the ends of the red line are equal? Q6 > I want know, after the SERDES RX and JESD204B RX, the data i get in FPGA is the ADC output data append 0 and OVR. is this understanding the right?
↧
