In the DESIQ or DESCLKIQ mode, the two differential input channels take in "exactly" the same signal; i.e. the two inputs are connected in parallel. Each differential input has a differential input impedance of 100 Ohm. Therefore, when connected in parallel, the effective differential input impedance is 50 Ohm. How, then, to design the optimum interconnect path from the differential amplifier (e.g. LMH6554) to the inputs of the ADC?
In the DESIQ/DESCLKIQ mode, it is unfortunate the ADC inputs are terminated internally rather than the designer being able to terminate externally (except the internal termination minimizes parasitic inductance and capacitance that board-level components and routing would introduce). If external termination was an option, a single, 100 Ohm differential resistor could be used at a suitable, compromise location to terminate both inputs, keeping the differential input impedance at 100 Ohm, and allowing the differential pair routing interconnect path from the differential amplifier to be 100 Ohm differential impedance. In this case, the two (one on each output leg) series Ro resistors at the output of the differential amplifier would be 50 Ohm and, with loose coupling, each trace in the differential pair routing would have a characteristic impedance of 50 Ohm.
However, because the effective differential impedance of the paralleled ADC inputs is only 50 Ohm, the two series Ro resistors at the output of the differential amplifier should each be 25 Ohm and each trace in the differential pair routing should have a characteristic impedance of 25 Ohm so that, again with loose coupling, the differential impedance will be 50 Ohm.
This 50 Ohm differential path to match the effective 50 Ohm differential impedance at the ADC inputs seems to be the optimum solution. Opinions, please.