Hi,
For this device your understanding of the clock rates is correct. You would supply a 500MHz clock to the ADC for a 500Msps sample rate and the DDR LVDS output clock would be 250MHz with a sample on the rising edge of the output clock and a sample on the falling edge.
Not all data converters are exactly like this, so you would need to check the datasheet carefully. Some other ADCs might output the LVDS DDR output clock at the full rate of the sample clock and output half the sample on the rising edge and half the sample on the falling edge - essentially pushing the DDR clock rate twice as fast in order to use half as many LVDS outputs (such as ADS4149 for example). And yet other devices might have a clock divider on the input clock so that the effectve sample rate might be half or a quarter of the clock you give to the ADC.
But for the ADS5404 i is as you describe.
Regards,
Richard P.