Dear.JIM The PLL was resolved from the customer. Customers have experience developing with ES sample version. Is there a register difference between the RTM version and the ES sample version? It is not output normally to generate CW by FPGA and measure DAC38RF83 output. If you generate a test pattern(K28.5, ILA, D21.5) in the FPGA and set the Reg value of the DAC38RF83 and verify it, there is no abnormality. It is necessary to confirm that the DAC38RF83 has an erroneous setting value. I want to get the DAC38RF83 reg setting value. The setting values are as follows. - Sampling Rate: 5440MSPS - CLK Input: 226.6666MHz(5440/24) - Interpolation: 24x - LMFS: 4421 (Because it is Dual CH, two 4421 are used.) - Lane Rate: 4.53333333Gbps * 8Lane - K: 4 - SYSREF CLK: 7.083333MHz Thank you.
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