Hello Yoshiki-san, Thanks for your post! The reason that the SCLK must equal a 1/2^n ratio of CLK in FSYNC Mode is that Frame-Sync is a continuous interface. This means that both the CLK and SCLK signals must be continuously running. If the SCLK frequency was a non- 1/2^n ratio of CLK, you would eventually run into a condition that caused you to miss data, either at the beginning or at the end of the data word. The more traditional SPI interface does not require a continous SCLK - in fact, you can send the SCLK signals in "bursts," so long as you send enough clocks to read all the data bits before the next sample is ready. In both modes, keeping SCLK/CLK to a 1/2^n ratio yields the best noise performance, but any other clock frequency will still allow the device to perform within the min/max specifications. Best Regards,
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