Hello Clancy! @1: EEPROM handling is currently not implemented; I'm just writing to device registers (OVUV1 to OVUV6, TLOOP_CFG, AFE_CFG, PHASE_CFG, CONFIG1, CONTROL1, CONTROL2, CONTROL3, CLCRC, CRC,CRC_CTL1) So I wouldn't expect a problem from that side. @2: I check with an oscilloscope; there are no spikes at the NRESET pin. The FAULTRES pin is a little more wobbly, but are easily within the 70% bounds given in the datasheet. @3: I increased the current limit on the power supply (from 350mA to 950mA @5V); now I see that the configuration is correct on the chip; but the readout of the angle is still only updated when I keep FAULTRES at LOW level. I currently do as follows: 1) FAULTRES -> HIGH 2) NRESET -> 100us 3) 6ms wait for "self-init" of chip 4) toggle FAULTRES 5) DIAG Mode -> write config -> NORMAL MODE -> read config 6) verify read config vs. expected config; if as expected (the same), then force FAULTRES to LOW. 7) periodically read STAT4, STAT5, STAT6, STAT7 and config (just to check that it is kept) with this sequence the angle in STAT5 is updated. If I skip step 6, I only get one angular value. My configuration (CRC calculated for read addresses): DEV_OVUV_1 = (CRC = 60, ResStatus = 0, OSHORTH = 0, OSHORTL = 0, EXTILIMTH_H1_2 = 5, EXTILIMTH_L1_2 = 5, EXTOUT_GL = 8, ADDR = 83) DEV_OVUV_2 = (CRC = 40, ResStatus = 0, DVMSENL = 5, DVMSENH = 5, TRDHL = 3, XEXT_AMP = 0, res = 0, ADDR = 107) DEV_OVUV_3 = (CRC = 52, ResStatus = 0, OOPENTHH = 7, OOPENTHL = 7, OVIZH = 3, OVIZL = 0, EXTOVT = 7, EXTUVT = 7, ADDR = 101) DEV_OVUV_4 = (CRC = 16, ResStatus = 0, FSHORT_CFG = 0, nBOOST_FF = 1, VEXT_CFG = 0, AUTOPHASE_CFG = 0, TEXTMON = 7, TSHORT = 7, res = 0, ADDR = 236) DEV_OVUV_5 = (CRC = 53, ResStatus = 0, res = 0, TOPEN = 7, res2 = 0, ADDR = 82) DEV_OVUV_6 = (CRC = 61, ResStatus = 0, LPETHH = 3, LPETHL = 3, res = 0, BOOST_VEXT_MASK = 0, IZTHL = 7, res2 = 0, ADDR = 233) DEV_TLOOP_CFG = (CRC = 27, ResStatus = 0, DKI = 4, SENCLK = 0, OHYS = 1, DKP = 4, MKP = 2, res = 0, ADDR = 166) DEV_AFE_CFG = (CRC = 28, ResStatus = 0, GAINSIN = 1, GAINCOS = 1, res = 0, ADDR = 194) DEV_PHASE_CFG = (CRC = 36, ResStatus = 0, PHASEDEMOD = 0, EXTOUT = 0, EXTMODE = 1, APEN = 1, PDEN = 0, EXTUVF_CFG = 0, ADDR = 87) DEV_CONFIG1 = (CRC = 61, ResStatus = 0, MODEVEXT = 2, SELFEXT = 0, res = 0, NPLE = 0, res2 = 0, ADDR = 190) DEV_CONTROL1 = (CRC = 16, ResStatus = 0, DIAGEXIT = 0, MEXTMON = 1, MAFECAL = 1, MIZUV = 1, MIZOV = 1, MEXTUV = 1, MEXTOV = 1, MFLOOPE = 1, MFOCOSOPL = 1, MFOSINOPL = 1, MFOCOSOPH = 1, MFOSINOPH = 1, res = 0, MFOSHORT = 1, res2 = 0, ADDR = 144) DEV_CONTROL2 = (CRC = 37, ResStatus = 0, ENEXTUV = 0, ENEXTMON = 0, ENBISTF = 0, ENIOFAULT = 0, ENINFAULT = 0, RDC_DISABLE = 0, res = 0, LBIST_EN = 0, ABIST_EN = 0, ADDR = 99) Status readout: DEV_STAT1 = (CRC = 39, ResStatus = 0, FOSHORT = 0, FGOPEN = 0, STAT = 0, FOSINOPH = 0, FOCOSOPH = 0, FOSINOPL = 0, FOCOSOPL = 0, FLOOPE = 0, EXTOV = 0, EXTUV = 0, EXTILIM = 0, FTECRC = 0, FCECRC = 0, FRCRC = 0, FLOOP_CLAMP = 0, ADDR = 129) DEV_STAT2 = (CRC = 0, ResStatus = 0, SORD = 0, SPRD = 0, res = 0, ADDR = 0) DEV_STAT3 = (CRC = 16, ResStatus = 0, FIZH1 = 0, FIZH3 = 0, FIZH2 = 0, FIZH4 = 0, FIZL1 = 0, FIZL3 = 0, FIZL2 = 0, FIZL4 = 0, OMIZ1H = 0, OMIZ3H = 0, OMIZ2H = 0, OMIZ4H = 0, OMIZ1L = 0, OMIZ3L = 0, OMIZ2L = 0, OMIZ4L = 0, ADDR = 132) DEV_STAT4 = (CRC = 31, ResStatus = 1, SOUTZ = 0, SOUTB = 1, SOUTA = 1, SFAULT = 0, IOFAULT = 0, FVDDOV = 0, FVCCOV = 0, LBISTF = 0, ABISTF = 0, FEXTMODE = 0, FTSD2 = 0, FVDDOC = 0, FBSTOV = 0, SPI_ERR = 0, FEXTMONL = 0, FEXTMONH = 0, ADDR = 31) DEV_STAT5 = (CRC = 28, ResStatus = 0, ORDANGLE = 393, ORDCLOCK = 0, PRD = 0, res = 0, ADDR = 65) DEV_STAT6 = (CRC = 62, ResStatus = 0, ORDVELOCITY = 16383, PRD = 0, res = 0, ADDR = 111) DEV_STAT7 = (CRC = 17, ResStatus = 0, REVID = 3, OPTID = 1, DEVSTATE = 1, FAFECAL = 0, res = 0, ADDR = 225) Controls: DEV_CONTROL3 = (CRC = 5, ResStatus = 0, EXTEN = 1, LPEN = 1, SPIDIAG = 0, reserved = 0, ADDR = 221) DEV_CLCRC = (CRC = 55, ResStatus = 0, ECCRC = 0, res = 0, ADDR = 79) DEV_CRC = (CRC = 38, ResStatus = 1, RCRC = 122, res = 0, ADDR = 15) DEV_CRCCALC = (CRC = 33, ResStatus = 0, CRCCALC = 122, res = 0, ADDR = 217) DEV_EE_CTRL1 = (CRC = 24, ResStatus = 0, EECMD = 0, res = 0, ADDR = 227) DEV_CRC_CTRL1 = (CRC = 53, ResStatus = 0, CRCCTL = 1, res = 0, ADDR = 122) DEV_EE_CTRL4 = (CRC = 32, ResStatus = 0, EEUNLK = 0, reserved = 0, ADDR = 186) DEV_UNLK_CTRL1 = (CRC = 2, ResStatus = 0, DEVUNLK = 240, res = 0, ADDR = 100) BR, Markus
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