Hi Jim, Thanks for your timely reply. I've made some progress from my last post, and I believe I am getting lane alignment properly now! I changed my JESD clock divider from an 8 to a 4 (setting the JESD clock to 312.5 MHz instead of 156.25 MHz.) The Disparity and code sync errors are no longer triggering on the DAC. I am, however, still getting errors for each of my four lanes complaining about: "write_error : Asserted if write request and FIFO is full" and "read_error : Asserted if read request with empty FIFO". I am clearing and polling these registers every two seconds while running my system. I've attached a new updated system timing diagram as seen by the logic analyzer core built into my FPGA showing the ILA sequence and data getting through. The TI datasheet on my DAC has practically no details about the FIFOs... my best interpretation of my errors is simply that something about my DAC timing configuration is still messed up. Is there any other insight that you could provide into those FIFO errors? Have you seen problems with them before very often? What are the typical issues at play in those cases? Thank you very much for your time, Kyle Harris
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