Hi Kawai,
Unlike the RD input on the ADS7263, the CONVST input does not need a clock edge to be recognized. The sample and hold switch opens with the application of the CONVST, going from sample to hold mode, regardless of the SCLK input. The actual start of conversion timing however, is dependent on the SCLK input. In order to achieve the maximum throughput, the CONVST input would be applied high on the falling SCLK edge so that the next rising SCLK edge started the conversion process. If your CONVST is synchronous with the rising SCLK, it will be the next rising SCLK edge that starts the conversion process. I'll send you an e-mail explaining it a bit further...