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Forum Post: TLV320AIC3256 Oversampling and decimation calculations

Hi TI,

I'm using the TLV320AIC3256 in a design that's connected to two digital microphones multiplexed onto the same input line.  My microphone specifications say that I can clock them between 1 and 3MHz.  I'd like to sample the audio at 48KHz into miniDSP_A and then pass it on to the OMAP via I2S.

I'm having trouble determining all the different clock and divider settings that I need to use.  Here's what I think that I've figured out so far:

  • Our MCLK input at the codec is set to 19.2MHz.  We pass this through the PLL (P=R=1, J=4, D=4800) and use it as codec_clk_in, which is now ~86MHz.
  • It seems that the only clock that can be used for the digital mics is adc_mod_clk.  Therefore we get that to 3.072MHz by setting NADC=2 and MADC=14.
  • Right now we have AOSR=64 to get a final ADC f_s of 48KHz.
  • We're decimating by 4x in the DSP and just hooking it directly up to I2S_out.

This seems like it should be right, but the audio is coming through very garbled.  I'll attach a sample of the audio once I find the upload button.

I'd appreciate any help with determining what clock settings we should be using.  Thanks!


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