Hello Craig,
The current datasheet states that both edges could be used to read out data, and as you mention, it doesn’t apply for fast SCLK frequencies due to data delays. However, it does apply for SCLK frequencies slower than 37.3MHz as illustrated in the following image for slower sampling rates:
Although datasheet timing diagrams imply that data should be read in subsequent falling edges for fast SLCK, the written explanation is missing this important distinction for SCLK frequencies faster than 37.3MHz, which apply to the ADS8881, ADS8861, and ADS8860. For example, the following diagram shows what you mentioned regarding the need to use subsequent falling edges to accommodate the data delays:
Therefore, in the current revision, besides of SCLK update, we will be including a clearer explanation in the datasheet regarding reading edges for fast and slow SCLK frequencies for the ADS8881, ADS8861, and ADS8860.
Thank you,
Rafael