Forum Post: ADS1278 sampling rate

Hi,

I am planning to use TI delta-sigma ADC ADS1278 in my design, where all the eight channels will be sampled simultaneously.

I have below queries: regarding ADS1278 master clock frequency and 

I am planning to use 27MHz clock frequency to have data rate of 105.469KSps. I also want to reduce the data rate by switching to lower clock frequency    All changes in clock frequency will be done only when sampling is disabled (SYNC# is high). Once appropriate clock is given to the ADC, sampling will be enabled by pulsing SYNC# to Low. So is this sequence right for changing the data rates of the ADS1278?? Please comment on this.

Also, although we have different data rates, but we will have anti-aliasing filter with lowest cut-off frequency  to take care of whole range of data rates. Hope that is ok.

Thanks and regards,

Rajesh