Hello Huck,
After performing some experiments with a DAC from the same family line, DAC8574, I've verified that the read accesses the DAC Channel register, which directly corresponds to the DAC output voltage. I've tried all configurations of L1, and L0, and all readback values are the same, verifying that all configurations access the DAC register, as opposed to the temporary register. Although the 'read' is not dependent on the L1, and L0 values, the 'write' value does need these to set up the correct mode. For my 'write' experiments I used L1=0, and L0=1. Below is some example pseudo code for the I2C writes and reads:
Example Write: Start SL ACKS Ctrl-Byte ACKS MS-Byte ACKS LS-Byte ACKS Stop
Example Read: Start SL ACKS Ctrl-Byte ACKS Sr SL ACKS MS-Byte ACKM LS-Byte ACKM Stop
Legend: ACKS - Slave ACK \ Sr - Restart \ ACKM - Master ACK \ SL-Slave Address
For your experiments, you can try L1=0, and L0=1, and perform an I2C write. If the DAC output voltage doesn't update with the correct output voltage, you should then verify the I2C write is valid, by ensuring that all ACKs are received. Once this is working, you can then try an I2C read, and verify the ACKs to ensure you are receiving a valid read.
Best Regards,
Matt
