Hi Mahdi
I apologize for the delay. In answer to your questions:
1)a) In the data manual, the noise floor density is given by -154.0 dBFS/Hz. I would like to know under which setting this has been obtained (input signal frequency and power level, considered bandwidth 1.8GHz or 3.6GHz?)
That measurement is done using AC coupled 50ohm terminated inputs (no input signal) in DES-I or DES-Q mode.
1)b) Is there any relationship between SNR and the noise floor level, in the sense SNR=154.0 dBFS/Hz + 10*log10(3.6e9) + input signal power in dBFS
That relationship exists, however the figure provided in the datasheet is without an input signal. The actual SNR achieved will depend on the amplitude and bandwidth of the input signal and the resulting rise of the noise floor.
2) The IMD3 seems to be very sensitive to the input frequency, for instance from Fin=2670MHz to Fin=2070MHz, the IMD3 changes by 10dB, is there an explanation for that?
For larger amplitudes and at higher frequencies, the internal Track and Hold circuit tends to limit the IMD3 performance. That is why the IMD3 performance improves as the signal level is reduced.
3) Does the internal pre-amplifier insert any kind of nonlinearity to the signal?
There is no "amplifier" included in the signal path, only a buffer stage to isolate the internal Track and Hold from the driving circuitry. As the buffer is an active device there is some potential non-linearity added at this stage which combines with the non-linearities of the other stages of the ADC (amplifiers and comparators).
4) The data manual provide only the INL and DNL curves for the Non-DES-I mode. Are they also similar for the DES mode?
INL and DNL are similar in the DES modes as in the non-DES modes. The key difference in the DES modes is that there can be residual (after calibration) mismatch in offset, gain, linearity and sample timing between the interleaved ADC cores. Offset and timing mismatch are usually the most noticeable. Offset mismatch can be further reduced by adjusting the I or Q channel offset register setting. Timing mismatch can be reduced by adjusting the DES Timing Adjust register setting.
I hope this is helpful.
Best regards,
Jim B