Hello,
I would like to provide the master clock for the DIT4192 directly from a clock distribution chip. But then SCLK, LRCLK and data coming from the ADC chip will have a delay of about 3ns compared with the direct clock signal because of a bus transceiver on the audio serial lines. In datasheet I find no information about the timing requirements of the master clock related to the audio serial input. Has someone experiences whether these 3ns offset could cause problems?
By the way, does someone know what exact function the separate master clock input has? Mainly I wonder what clock determines the clock quality of the AES output signal, the master clock, SCLK or LRCLK?
It would be very nice if someone could give me some more information please.
Best wishes
Ralf