Hello Suresha,
I had some time this morning to go through your calculation spreadsheet. Here are some notes:
Since you're looking at the IDAC matching I have to assume this is for a 3-wire RTD. In that case the VREF voltage is 2*IDAC * RREF as described in TIPD120, so update cell C6 to show this correctly.
Other than that, the theory behind the rest of the spreadsheet is very sound and I believe this takes a conservative approrach to the final accuracy. Here are some notes:
1.) Max offset drift you've listed in C35 is only 6uV for a PGA gain =1, the minimum PGA gain you'll be using is 2 and highest is 16. For the higher gains the offset drift will go down resulting in less effect.
2.) While higher PGA gains result in less offset drift, they result in higher gain error. The 0.03% spec you've used in C37 is only for PGA gain of 128 which you will not use.
3.) You could try to reduce the effects of C47 by "chopping" the inputs back and forth as suggested in TIPD120.
Otherwise I think you've done a great job and agree with your calculations.
Please let me know if we can help with anything else.