I did some more testing and found that NDAC, MDAC and DOSR correctly work, but that CODEC_CLKIN is at 40 MHz - instead of the expected 98 MHz from the PLL. I currently use the following code to get the PLL up: dac_writePageAddress(0, 4, 0x0B); // 0x8 (PLL_CKLIN = GPIO1) + 0x3 (CODEC_CLKIN = PLL_CLK) dac_writePageAddress (0, 6, 0x04); // 0x4 (J-VAL 4) dac_writePageAddress16(0, 7, 0x23C0); // 0x23 (D-VAL MSB), 0xC0 (D-VAL LSB) = 9152d dac_writePageAddress(0, 5, 0x91); // 0x80 (PLL on) + 0x10 (PLL divider P = 1) + 0x01 (PLL multiplier R = 1) (scripted, that would be "w 30 04 0B 91 04 23 C0"). Is there anything that I missed? I double checked the datasheet but didn't find anything else...
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