Here are the config files. They are based on your reference configs which you have provided with the TSW54J60 GUI. For the test-setup i’m using the TSW54J60 on the VC707 (FMC2 J37). I’m using a 122.88MHz reference clk on LMK CLKin (J6). Then the LMK is supplying all necessary clks. Also the 122.88MHz glblclk and the 491.52MHz refclk for the Xilinx JESD204b IP (CLK_LAO_0P/M and FPGA_JESD_CLKP/M). The ADS54J60 JESD is running in 8224 mode + Scrambling. I will also try to get the TSW14J56EVM to do tests with that one too. Best regards! Martin (Please visit the site to view this file) (Please visit the site to view this file)
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