Hi Kl The errors on specific lanes could be due to inadequate serial data eye opening at the FPGA GT receivers. 1) Try decreasing or increasing the ADC12J4000 serializer pre-emphasis setting (Register 0x040h, Bits 3:0) to see if the error behavior changes. The current setting you are using may be too low or too high for the link distance and PCB dielectric material of your board. 2) Try decreasing the clock rates. Instead of 4000 MHz, try a lower ADC DEVCLK frequency. (reducing all related clocks by the same ratio) If reducing the serial interface bit-rate eliminates the errors they are most likely due to issues with signal quality on those 2 lanes at that speed. I hope this is helpful. Best regards, Jim B
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