Hi Jim,
Thank you for the post--you beat me to a solution by just a few hours! I can confirm that the new .bit file does work fine, and now allows properly aligned capture in non-DES I+Q mode up to 32k samples.
As possible help to others, I have also posted my own fix (Please visit the site to view this file) to the Verilog firmware should people wish to recompile the Virtex-4 from sources (like we're doing in PlanAhead 13.4).
If you look at my amended code, you'll see that the basis for the fix is to separate the FIFO read enable registers into individual I and Q controls. This allows the I samples FIFO to be read independently without inadvertently asserting read enable on the Q FIFO. Otherwise (the existing code) would read both FIFOs at once, and effectively skew one channel by the capture size.
Regards and thanks,
Bernard Gunther
[quote user="Jim Brinkhurst84999"]
Hi Bernard
Please try this file for that board. (Please visit the site to view this file)
It should resolve the issue. If it does not, please let me know.
This newer file will be included in a new Wavevision 5 installer coming soon.
Best regards,
Jim B
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