Hi Shams,
Regarding your comment on noise performance:
[quote user="shams iqbal1"]and if we go for 2.5 hz update rate then we can get 20bit resolution which is noise free but above then only on 10hz sample rate its noise free bits reduced to 17-bits [/quote]
The ADS1256 should be giving you 20 bits noise-free resolution at 10 SPS. Table 3 tells you the possible noise-free performance (measured with shorted inputs). In most applications there will be some noise degradation because we don't care to measure shorts, but real signals which have noise.
Note that the noise-free resolution goes down with the PGA gain. However, for each binary increment of gain, the signal amplitude is doubling and the noise-free resolution decreases by less than 1 bit (Noise increases, but not as much as the signal amplitude). Therefore, you are actually gaining resolution as the PGA gain increases.
Regarding your question on the ADS1252:
[quote user="shams iqbal1"]if i pulled high serial clock line for five drdy cycles and released serial clock line to low then what should i consider to that what is the current drdy/dout function status and how to calculate adc clocks for one drdy cycle basically i want to use timer counter to determine dout status for data reading and once it is synced with timer so i can easily read the data from it while adc clock is being supplied from micro-controller so clock syncing procedure will work with out any problem and free up the processor for other tasks[/quote]
Holding SCLK high for 5 clock cycles resets the modulator, which is what you're trying to do. The reset happens about on the falling edge of SCLK. Actually, reset will be on the first falling edge of CLK after the falling edge of SCLK. So unless your SCLK is derived from the CLK, you'll know within one CLK period when the reset happens.
A time "t14" after reset occurs (t14 = 2042.5 * CLK) is when the first /DRDY pulse occurs. However, data is not valid until the 6th /DRDY pulse because this is not a single-cycle settling device like the ADS1256. Therefore, you'll need to wait an additional five t_DRDY time periods. So your first timer will start on the falling edge of SCLK, and count down from (2042.5 + 1 + 5*384) * CLK or 3,963.5 CLK periods. Then every following timer needs only to count 5 (or 6) t_DRDY time periods or about 1920 (or 2,304) CLK periods.
Best Regards,
Chris