Problem solved. Found that if I use USB bus power to power up ADS1274 core and I/O together and then apply analog power to ADS1274 approximately 0.2 seconds after USB bus power(using RC time delay circuit) I get consistent clean “Global Power-on Reset”. When FX2 starts up from EEPROM it puts its 8051 CPU in reset while serial engine logic loads firmware into RAM and then releases the CPU which starts to configure its I/O pins and drive I/O pins on my CPLD which in turn can cause activity on ADS1274 pins. I do not have logic analyzer but assume that the time to put CPU in reset, load ROM and release CPU something greater than about 0.2 seconds is why it works. Anyway that’s my theory but it works. Attached images of quality of signal conversion. Thanks for Help Greg Jim
