I have a ADS1274EVM early version(OPA1632's). Serial data (SPI mode)converted to byte parallel format by CPLD sent to Cypress FX2LP USB2.0 FIFO into PC. I have two prototypes call them "System 1" and "System2". "System 1" has high quality analog linear power supplies with digital supply coming form USB bus power. Power sequence for "System 1" plug in USB cable 3.3 volt reg on FX2 board powers FX2 ,3.3 volt powers ADS1274EVM I/O with your on-board 1.8 volt reg powers ADS1274 core, switch on analog supplies. No problems all four modes work up to 27 MHZ clock speed SCLK 1/2 CLK.
"System 2" all power analog and digital from sequenced linear power supplies. Power sequence for "System 2" lift jumper J13 on EVM(disable on-board 1.8v reg.) apply 1.8 volts to core, wait ~ 2 seconds a apply 5 volts to 3.3 reg. on FX2 board and EVM I/O.wait ~ 2 seconds apply analog power. "System 2" has corrupted data sometimes after power up, and sometimes it's OK after power up. Is there a way to reset the ADS1274 after power up? If it starts up clean it runs 100% like "System 1". It seems like I have a ground bounce or glich in the supplies at start up which I can not find. Both systems use same hardware and software accept for the power supplies. I flush the FIFO's and apply SYNC NOT before start of each acquisition. "System 1" uses LM317 and LM337 Regs. "System 2" uses LM78XX and LM79XX regs. One poor solution to problem is to turn "System"2 on and off until I get a "clean reset" on ADS1274. The CLK is active at power up. If I enabled CLK after Power up would I get a reset. Attached images of problem. Thanks Jim.
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