Hello, I am using three ADC08D1520 ADCs in Non DES, 2:1 DEMUX Mode and drive them with 3 matched (low jitter and in SYNC) 1.5GHz clocks. I need to make sure all 3 ADCs are synchronized and there is NO phase error when sampling the analog inputs to 3 ADCs. I have tied the pin-52, DRST_SEL to GND to use the DCLK_RST+/- as differential reset to 3 ADCs. According to datasheet figure 8, page (24/59) and page (18/59) the tHR, tSR should be met to reset the ADC (in DDR mode) properly. I am using ADC clk_in=1.5GHz so would need to meet the tSR=90ps and tHR=30ps based on page (18/59) and tPWR(min)=4 (666.6)ps=2.67ns. I wanted to use an asynchronous LVDS DIFF pair to drive all 3 ADCs DCLK_RST+/- inputs at the same time after power-on and whenever needed, as noted on page 42/59 which says DCLK_RST could be asserted ASYNC with respect to input clk (1.5GHz in my board) But now I am worried about meeting the tSR & tHR by driving it ASYNC to ADC input clock. I think if I drive the DCLK_RST lines ASYNC it doesn't guarantee the Reset since tSR & tHR could be missed. I am not sure why datasheet says (page42/59) DCLK_RST can be driven ASYNC with input clock and also it mentions tSR&tHR should be taken into account. Your suggestions, thoughts and workaround all appreciated. Thanks, -Reza
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