Hi Nishanthi
If you have not done so already, please review the information in AN-2132: Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature found here: http://www.ti.com/litv/pdf/snaa073f
Section 3.2.1, Step #3 describes the proper procedure to choose the right Delay Reference Clock setting. Once this step is complete, then the Select Phase bits should be adjusted to find the best alignment between the Master and Slave DCLK outputs.
I hope this is helpful. Please let us know if you have additional questions.
Best regards,
Jim B