Hi, Kenji-san
"SHIGH-WIDTH" means the number of clock cycles width of sampling clock, so SHIGH is an internal sampling clock for AUX_ADC. For a better understanding of AUX_ADC, I'll give you an example for the processing of AUX_ADC and relation to Figure 10-16 as below.
With 0x37 of register value for the register 0x364 (CONFIg135),
SHIGH_WIDTH = 15
NO_OF_SAMPLES_AVERAGED = 8
NO_OF_SAMPLES = 8,
AUX ADC will output data on SDOUT with 335.5 clock cycles after a value of 0x37 is written to the register 0x364, where 335.5 = 48.5 + {(n-1)*(26+SHIGH_WIDTH)},
n = 8
SHIGH_WIDTH = 15,
and 48.5 = (20+1) + (26+1.5) from Figure 10-16 AUC ADC Timing diagram.
I hope this example can help you to understand better.
Thanks,
KW