Sir:
We have made the following the hardware changes to synchronize codecs A and B on AIC34.
Connect GPIO1_A to GPIO2_A and GPIO2_B. We are generating 12.288M clock on GPIO1_A using the PLL. The PLL uses MCLK of 19.2M to generate 98.304M at PLL_OUT. This is then routed to GPIO1_A and eventually to GPIO2_A and GPIO2_B.
We are following the sequence below to program the registers to synchronize the codecs A and B; however, we are not getting the correct clock on GPIO1_A.
Is there any particular sequence that we need to follow to program the registers? Could you please help?
Thanks a lot!
Cheers,
Mushtaq
Step 1: configure codec A, disable codec clocks & start pll
- CLKDIV_IN_A = GPIO2_A (i.e. disabled)
- Q_A = 2
- CODEC_CLK_A=CLKDIV_OUT
- CLKOUT_IN_A=CLKDIV_IN_A
- CLKOUT_A = CLKOUT_IN_A / 8 (M=2, N=8)
- GPIO1_A = CLKOUT_A
- CODEC_CLK_A = CLKDIV_OUT_A
- PLL_IN_A = MCLK_A
- set pll so that PLL_OUT= 48000*256*8 = 98304000 Hz
- PLLDIV_OUT = 12288000 Hz
- enable PLL
- fsref=48000
- BCLK_A = output
- WCLK_A = output
- Bus in I2S mode.
- NDAC=6, NADC=6
Step 2: configure codec B.
- CLKDIV_IN_B = GPIO2_B
- Q_B = 2 (CLKDIV_OUT = CLKDIV_IN)
- CODEC_CLK_B = CLKDIV_OUT_B
- bclk, wclk = input, set fsref & all the codec configurations for I2S mode at 8kHz.
- wait 100mS to ensure PLL_A has stabilized.
Step 3: enable the clock
- Enable the clock -- set CLKMUX_OUT so that CLKOUT_IN = PLL_OUT. This will start GPIO1_A running at 12.288MHz, Now both codecs would be in synchrony.