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Channel: Data converters

Forum Post: RE: ADC3562: Regarding the timing when Sample N sampled by the...

Hi Oda, I agree, this is confusing. I am checking with design. Please give me a few days to respond back. Regards, Rob

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Forum Post: RE: ADS131M08: input short by CFG register settings

Hi Saad, If the gain you set in ADS131M08 is higher than 4, you will have to keep the input voltage less than AVDD-1.8V=3.3V-1.8V=1.5V. If your gain is less or equal to 4, the input voltage to AIN pin...

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Forum Post: [FAQ] Which TI devices support the HART protocol?

Part Number: AFE881H1 Other Parts Discussed in Thread: DAC161S997 , DAC161P997 , DAC8750 , DAC7750 , DAC8760 , DAC7760 , DAC8771 , DAC8775 , DAC8740H , DAC8741H , DAC8742H , , AFE781H1 , AFE882H1 ,...

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Forum Post: RE: ADC3910D065: DCLK/FCLK termination

Thank you.

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Forum Post: RE: ADS1247: START and SYNC Commands

Thank you, Bryan, I do see similar behavior, but my question is more geared towards the sequence that I am proposing. In short will adding sync after the start and waiting for a subsequent conversion...

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Forum Post: RE: [FAQ] AFE881H1: Which TI devices support the HART protocol?

TI has many DAC devices that are compatible with the HART Protocol. Some devices provide a range of analog outputs. These devices can output a voltage or current with the HART frequency-shift-keyed...

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Forum Post: RE: AFE4400: Unable to drive the photodiode normally, unable to...

Hello Wu, I apologize for the delay in response. Are you testing with the photodiode connected or disconnected from the board? If you remove the photodiode and run the diagnostic mode, do you get an...

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Forum Post: RE: ADS131M08: input short by CFG register settings

Hi Dale, As said before , the gain is 128. The bridge excitation is the same as AVDD of the ads131 which means that we must have AVDD to be 3.6V at least to allow for (3.6-1.8=1.8V) of the bridge mid...

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Forum Post: RE: TSC2007: The TSC2007 cannot communicate with the AM6234 via I2C

Hi, So, if your A0 and A1 pins are grounded, I believe the first 7 bits of the address are defined as 1001000 (0x48). But, if you tie to the 3.3V supply, the address will be 1001011, which would be...

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Forum Post: RE: ADS1247: START and SYNC Commands

Hi George Sarkees, The SYNC command just restarts the conversion, basically the same as taking START high. I don't know why this would change the behavior of your system. Also, the datasheet...

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Forum Post: ADS1261: Wokring with ADS1261 connected to ESP32

Part Number: ADS1261 Tool/software: Hi everyone, I’m working on a project where I designed a custom PCB that uses two ADS1261 ADCs to measure differential voltages between 16 electrodes. Here’s my...

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Forum Post: RE: AMC3336-Q1: HGND connected to AGND

Hi Michael, What current magnitude and voltage level do you plan to sense to? I'm curious why you would choose this configuration as opposed to sensing the current using a shunt resistor. Either way...

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Forum Post: RE: DAC8571: Low power and fast settling

Hi Katlynne-san, Thank you for your support. We explained the following to the customer, and they understood. " It is likely that when the phase margin is low power mode, the response is slowed to...

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Forum Post: RE: ADS1261: Wokring with ADS1261 connected to ESP32

Hi Balazs Hazi, Can you provide logic analyzer captures of the data communication during the initialization? Please include DIN, DOUT, SCLK, CS, DRDY, RESET, START, and PWDN -Bryan

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Forum Post: RE: ADS7066: data acquisition phase and necessity of input drive...

Hi, Yolanda! Thank you for your reply. I'm relieved to see that my understanding is correct. Let me confirm something further. If I extend the cycle time by changing the OSC_SEL and CLK_DIV[3:0]...

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Forum Post: ADS1298: ADS1298 - No DRDY or CLK signal after power-up

Part Number: ADS1298 Tool/software: Hello, I am working on a custom breakout board using the ADS1298, and I am facing an issue at startup. When I power the board with ±5V and set CLKSEL HIGH as well...

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Forum Post: RE: ADS131M08: input short by CFG register settings

Hi Saad, The recommended AVDD is between 2.7V to 3.6V as shown in the following table from the datasheet. The performance were tested and specified under this condition. The resistor can not change...

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Forum Post: RE: DAC124S085: DAC124S085 : Linux drivers writes command to...

Hi Varsha, In your analyzer 0xC2 is being sent as the MSB. If you look at the time scale, time is increasing as you move left to right meaning that the data to the left is the first data being sent...

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Forum Post: RE: DAC7574: DAC pulse generator with a 1uS rise/fall time

Hi Gopi, What is the high and low voltage level of the pulse? And what is the frequency of the pulse? How are you wanting to control the pulse? SPI, I2C, or something else? Best, Katlynne Jones

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Forum Post: RE: AFE4400: Unable to drive the photodiode normally, unable to...

Thank you, I found that the problem may be caused by the reverse connection of the photodiode. It has been resolved now

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