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Forum Post: ADS4245EVM CMOS mode

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Hello,

I have an ADS4245 EVM.  I want to use CMOS mode on this board which output from J1.    In order to use CMOS mode, I just follow the datasheet 'User's Guide ADS42xx EVM' on page 9.  Installed 'SN74AVC16T245' to U12 and U13; removed soldered resistors RN5 to RN12; and shunt JP26 and JP27.  And then connect JP14 to 2's comp CMOS.    All other connections are default.   

After I connected to 125MHz clock and 1MHz signal.  I don't see any output from J1.  and the J1 pin 39 has a clock output which looks like a triangle form and peak to peak is about 25mV.    Do I miss anything to run CMOS mode?

Thanks!

Zaidi 


Forum Post: RE: ADS1282 Filter Magnitude Response

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Hi Ragon,

Figure 46 should  represent the overall filter response of the cascaded SINC + FIR stages 1-4. Here was my result compared to Figure 46:

When I look at the FIR filter stages separately, I see similar responses to what you describe. However, I see the first two stages rolling off when stage 3 is peaking.

Regards,
Chris

Forum Post: RE: TSW1400EVM CMOS interface

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Hi,

The user guide will be updated soon. For AFE7070EVM interface with TSW1400, please refer to attached slide. This is a quick user guide for the setup.

Thanks,

KW

(Please visit the site to view this file)

Forum Post: RE: Source code DSP TMS230 for the MMB0 with ADS1299 EEG FE

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Sorry—yes, the email address in my profile will be fine.

Thank you!

Forum Post: RE: TLV320AIC11: could this be used to drive a Piezo speaker

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I don't think so, for the reasons that I mentioned previously. You need one of our class D (or AB) Piezo drivers like the TPA2100P1.

Forum Post: RE: ADS1259 Read Data Continuous Mode

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I'll take note of that. Thank you for sharing!

Best regards,
Chris

Forum Post: RE: ADC12D1800 Development board FPGA LVDS parllel interface code

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Hi Stephen,

We do not use IDELAY for incoming data is because our board has been designed very carefully to match all the data lanes and we do not have any data capturing issues due to trace length mismatch. The main purpose of the Reference Board is to show the performance of the ADC and we are not constrained on board space, so we have the luxury to match trace lengths.

Kind regards,

Marjorie

Forum Post: RE: TVP5158

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Well... limited :)

We will try to answer questions whenever we can but if the issue requires any sustained debug/analysis then it will likely not be supported.

These devices should not now be recommended for new designs.

The EP version is available still. Sorry for the confusion.

BR,

Steve


Forum Post: RE: ADS 1248 Data Acquisition as RTD

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Hi Ashwak,

Welcome to the forum! The ADS1248 takes a differential measurement from one analog input to another. It is not clear how you are connecting your inputs, so if you send me your schematic it would be helpful.

If you want to just measure your RTD and let's say you have it connected across AIN0 and AIN1. You assign the MUX to connect AIN0 to AINP and AIN1 to AINN (default settings). The voltage measured will be relative to the voltage drop across the RTD.  If you use a current excitation for the RTD, Ohm's Law can be applied to find the resistance of the RTD.

Best regards,

Bob B

Forum Post: RE: ADS1299 Evaluation Module Setup

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Hi Melanie,

Thanks for the explanation!

Therefore, a single-ended measurement should use the REF_ELEC as the negative input to all of input channels. This can be done by routing REF_ELEC to the SRB1 pin and setting the appropriate registers in the ADS1299.

Another alternative to route REF_ELEC to the negative channel inputs is to remove the jumper on (1-2) of JP25, and tie REF_ELEC to pin 1 only. Then, place a jumper on the appropriate pins of J6 (9-10, 13-14, 17-18, 21-22, 25-26, 29-30, 33-34). One advantage to doing this is to improve common-mode rejection as both the (+) and (-) inputs to each channel should see nearly the same input impedance to the ADS1299.

For the BIAS_ELEC, the intention behind this feature is to drive patient to a known potential, similar to the way the bias potential known as "Right Leg Drive" sets the common-mode of the patient in an ECG application. The BIAS_ELEC is generated internally and set to mid-supply. JP25 on the ADS1299 EVM allows you to route this bias potential to the (+) inputs (shorting 3-4), or the (-) inputs (shorting 1-2). If (5-6) are shorted, this BIAS_ELEC is shorted to the REF_ELEC and fed back into SRB1 pin of the device.

Since you are planning to use your own reference signal from the REF electrode in your diagram, you simply need to disconnect (5-6) on JP25, and connect your reference electrode in either of the two methods I described earlier.

Do you plan to bias the patient as well?

 

Regards,

Forum Post: RE: AD1118 Internal temperature deviations

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Hi Bob,

thank you very much for the fast response.

I already have downloaded this document . It looks like  that you are right and there is difference between the case, pcb and ambient temperature.

When I measure the PCB temperature close around the ADS1118 it is always lower then the temp on the case.

PCB temp: 33.0-33.4

ADS1118 Case temp: 34.3C

Internal temp sensor : 36.3125 C

I any case the ADS1118 is the most warmed up place on this part of the pcb ?!?

I am using the MSOP 10 Package.

In past projects I have used the LTC2480 from Linear , but the sampling rate is to low so I decided to use the ADS1118 which is very easy to implement. But with the temp sensor of the LTC2480 very accurate internal measurements are possible with minimal deviations compared to the "outside" temperature.

It looks like we will have to redesign our pcb with more GND copper around.

Will sent you pcb pictures soon.

Best regards

Kresimir

Forum Post: RE: TVP5150AM1 Pin9 PCLK/SCLK

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The current datasheet is correct.

Does their use case set this to a different value?

BR,

Steve

Forum Post: ADS4229 input clock to output clock delay variation

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I have a situation where I am using multiple ADS4229 ADCs to connect to different FPGAs and need the sampled data to arrive at each FPGA on the same clock edge, and assume the FPGAs are all phase locked.  The datasheet shows that tPDI, the clock propogation delay can vary by as much as 2.5ns which is quite a lot. I assume this is over a temperature variation, but I am not sure if this also include device-to-device variations as well. I would expect that two different ADS4229s at the same temperature would have a tPDI difference of picoseconds, not nanoseconds, but I could be wrong - this is not in the datasheet. Does anyone know what the maximum  device-to-device variation of tPDI and tSU could be if both devices are at roughly the same temperature?

Forum Post: RE: ADS8363 pseudo-differential resolution difference?

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Hi Jimmy,

Yes, you still have the full 16-bit range available when using the ADS8363 in pseudo-differential mode.

Forum Post: RE: ADS1278 sampling rate

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Mr Kumar -

Since you are interrupting the clock, we would recommend the following sequence (refer to pg 27 for future information)

  1. SYNC pin low
  2. Switch CLK frequency or change source.
  3. Once clock is stabilized, bring SYNC pin high again.
    1. After digital filter has settled, the DRDY pin will go low indicating valid data is ready.

Forum Post: RE: Inputs to ADS6445EVM and Altera FPGA interfacing

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Hi,

You will need some kind of signal conditioning circuit to shape your signal to the requirements for the data converter input.  The majority of our  customer applications do not include an input bandwidth down to DC or 0Hz, so the default configuration of our EVM is usually transformer coupled.  If the input circuit must include a bandwidth down to DC, then a transformer is not an option and an amplifier circuit is the usual choice.    in your case, a signal of < 100Hz is pretty much a DC signal compared to the bandwidth of the usual transformer coupled input. 

The THS4509 that is included on the ADS6445 EVM (on one of the four channels, not on each of the four channels) would be as good a choice as any as far as i know.  Note that the default circuit around that amp on the EVM is still AC coupled with series AC coupling caps, so you would probably still have to do some soldering to the EVM to set the amp up for the way you want it.  There is a different E2E forum here for the high speed amplifier group that can help with questions about the design of the amp circuit. 

The goal of the signal conditioning you need to do is to scale your signal to be less than the data converter's full scale range of 2V peak to peak differential, and to have the level of the signal shifted to the desired common mode voltage of 1.5V.  If a signal is AC coupled, then the shifting to the VCM voltage is easy with just connecting the VCM voltage to the common point of the termination resistors or to the center tap of the transformer coupling.  But if DC coupled and using an amplifier, the level shifting can be done with a common mode input to the amp if the amp has such an input - which the THS4509 does.

in your case, your signal is larger than the data converter full scale range, so you need attenuation instead of amplification.  Attenuating the signal is easy enough with a resistor divider, but the level shifting is still an issue so I think the amp path on the EVM is still the easiest option with some soldering of components around the amp circuit on the EVM.

If you want to try the high speed amplifier forum for specifics on the THS4509 or advice on a potentially better option, I could move this post over to their forum or you could repost there. 

For the choice of data converter EVM, do you want a device with a serialized LVDS output on one or two LVDS pairs like the ADS6445 EVM, or would you find it easier to create your FPGA firmware around a simpler parallel bus of dual-data-rate LVDS pairs such as the ADS6145 or ADS4145 EVM?  The ADS4145 EVM also has the THS4509 amp.

Regards,

Richard P.

Forum Post: RE: ADS1282 Filter Magnitude Response

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Chris,

Thanks.  Your result looks right.  I will revisit my analysis by cascading the Sinc filter and filter stages 1 & 2 with stages 3 & 4.  Apparently my assumption that the initial stages did not significantly affect the results is incorrect.  I'll let you know about the outcome.

Ragon

Forum Post: RE: TSW1400EVB Source Code

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Yes, you understand.  My email is <david.mcgaw@dartmouth.edu>.  Thanks for the explanation of the trigger state machine.  It may be possible to retain that and just modify the capture code to run as a circular buffer.  I can keep you apprised of our progress.  Thank you.

Forum Post: RE: Mic input noise with AIC3204 and AIC3254

Forum Post: ADS5281 ..

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Hello ,

can anyone help on this please,

I am working on project named 'Data Acquisition System'. here I am using ADS5281 8 channel and 12 bit output , here output of ADS5281 will be differential signal output(Lvds) Is there any way I could configure ADS5281 to produce output in single ended signal.

Reason why i am concerned is while interfacing to fpga i wanted to decrease number of pins that to be connected to fpga if it is single ended signal i can make lot difference in the pin count  i can tie all neutrals to 0 

Thanks in Advance 

Sahitya Venkatayog

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