Hi Chase, I tested you file with the FPGA simulator, the PRBS checker locks after several samples and then remains locked. PRBS checker works. Your data sequence is perfect. I'm trying now to replicate what you did to generate the PRBS samples. I modified my scripts to write 0x02 to register 0x09, i.e. enabling pattern synchronization on all channels. This means, the PRBS pattern generator doesn't work at all without channel synchronization. Could you confirm this? Anyway, with synchronization enabled the data looks far better, finally all the bits "almost" show a shift register behavior. However, the PRBS checker still doesn't lock... I checked the data waveforms, and I still saw something wrong happens. During the shift, some bits "disappear" and then "reappear" later in time. I thought about a bit error in the interface, however all the channels A,B,C,D always show the very same value, which would be not very probable if the problem was a borderline bit sampling. Again, all other patterns are always fine with zero errors... I'm operating at 49.5 MSps. I could try to reduce the sampling rate to see if the problem is related. What sampling rate did you use for the tests? What is your advice? Andrea
↧